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1. WO2021113000 - METHODS OF FORMING CHARGE-BLOCKING MATERIAL, AND INTEGRATED ASSEMBLIES HAVING CHARGE-BLOCKING MATERIAL

Publication Number WO/2021/113000
Publication Date 10.06.2021
International Application No. PCT/US2020/058754
International Filing Date 03.11.2020
IPC
H01L 27/11582 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
1158with source and drain on different levels, e.g. with sloping channels
11582the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/1157 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11568characterised by the memory core region
1157with cell select transistors, e.g. NAND
H01L 29/66 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
H01L 29/423 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
H01L 29/792 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
792with charge trapping gate insulator, e.g. MNOS-memory transistor
CPC
H01L 27/11565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11565characterised by the top-view layout
H01L 27/11582
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
1158with source and drain on different levels, e.g. with sloping channels
11582the channels comprising vertical portions, e.g. U-shaped channels
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • CHEUNG, Pei, Qiong
  • XU, Zhixin
  • FANG, Yuan
Agents
  • KENADY, D., Brent
Priority Data
16/704,17605.12.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHODS OF FORMING CHARGE-BLOCKING MATERIAL, AND INTEGRATED ASSEMBLIES HAVING CHARGE-BLOCKING MATERIAL
(FR) PROCÉDÉS DE FORMATION DE MATÉRIAU DE BLOCAGE DE CHARGE, ET ENSEMBLES INTÉGRÉS AYANT UN MATÉRIAU DE BLOCAGE DE CHARGE
Abstract
(EN)
Some embodiments include a method of forming an assembly. A first stack of alternating first and second tiers is formed over a conductive structure. A first opening is formed to extend through the first stack. A sidewall of the first opening is lined with a first liner material. The first liner material is converted to a first charge-blocking material. Sacrificial material is formed within the first opening. A second stack of alternating third and fourth tiers is formed over the first stack. A second opening is formed to extend through the second stack to the sacrificial material. A second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. The sacrificial material is removed. Charge- storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. Some embodiments include integrated assemblies.
(FR)
L'invention concerne, selon certains modes de réalisation, un procédé de formation d'un ensemble. Un premier empilement de premier et second étages alternés est formé sur une structure conductrice. Une première ouverture est formée à travers le premier empilement. Une paroi latérale de la première ouverture est revêtue d'un premier matériau de revêtement. Le premier matériau de revêtement est converti en un premier matériau de blocage de charge. Un matériau sacrificiel est formé à l'intérieur de la première ouverture. Un second empilement de troisième et quatrième étages alternés est formé sur le premier empilement. Une deuxième ouverture est formée à travers le second empilement jusqu'au matériau sacrificiel. Un second matériau de revêtement est formé à l'intérieur de la seconde ouverture, est gravé de manière anisotrope, et est ensuite converti en un second matériau de blocage de charge. Le matériau sacrificiel est retiré. Un matériau de stockage de charge, un matériau diélectrique et un matériau de canal sont formés adjacents au matériau de blocage de charge. Certains modes de réalisation de l'invention portent sur des ensembles intégrés.
Also published as
Latest bibliographic data on file with the International Bureau