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1. WO2021112247 - NON-VOLATILE STORAGE DEVICE, NON-VOLATILE STORAGE ELEMENT, AND MANUFACTURING METHOD FOR SAID NON-VOLATILE STORAGE ELEMENT

Publication Number WO/2021/112247
Publication Date 10.06.2021
International Application No. PCT/JP2020/045325
International Filing Date 04.12.2020
IPC
G11C 14/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
14Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
H01L 21/8239 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
H01L 27/105 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
H01L 21/8244 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8244Static random access memory structures (SRAM)
H01L 27/11 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
11Static random access memory structures
H01L 27/11507 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11502with ferroelectric memory capacitors
11507characterised by the memory core region
Applicants
  • 国立大学法人東京工業大学 TOKYO INSTITUTE OF TECHNOLOGY [JP]/[JP]
Inventors
  • 角嶋 邦之 KAKUSHIMA, Kuniyuki
  • 舟窪 浩 FUNAKUBO, Hiroshi
  • 大見 俊一郎 OHMI, Shun-ichiro
  • モリナ レイエス ジョエル MORINA REYES, Joel
  • 藤原 一郎 FUJIWARA, Ichiro
  • 堀 敦 HORI, Atsushi
  • 清水 荘雄 SHIMIZU, Takao
  • 中村 美子 NAKAMURA, Yoshiko
  • 三村 和仙 MIMURA, Takanori
Agents
  • 青木 篤 AOKI, Atsushi
  • 三橋 真二 MITSUHASHI, Shinji
  • 出野 知 DENO, Satoru
  • 高橋 正俊 TAKAHASHI, Masatoshi
  • 古賀 哲次 KOGA, Tetsuji
Priority Data
2019-21996604.12.2019JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) NON-VOLATILE STORAGE DEVICE, NON-VOLATILE STORAGE ELEMENT, AND MANUFACTURING METHOD FOR SAID NON-VOLATILE STORAGE ELEMENT
(FR) DISPOSITIF DE STOCKAGE NON VOLATIL, ÉLÉMENT DE STOCKAGE NON VOLATIL, ET PROCÉDÉ DE FABRICATION DUDIT ÉLÉMENT DE STOCKAGE NON VOLATIL
(JA) 不揮発性記憶装置、不揮発性記憶素子及びその製造方法
Abstract
(EN)
The present invention provides a non-volatile storage element and a non-volatile storage device that use a ferroelectric material, can be embedded in advanced CMOS logic, and are excellent in low power consumption and high reliability, and especially in data rewriting endurance. The non-volatile storage element at least has a first conductive layer, a second conductive layer, and a ferroelectric layer that is constituted by a metal oxide and is located between the first and second conductive layers, and a buffer layer having oxygen ion conductivity is present between the ferroelectric layer and the first conductive layer and/or the second conductive layer. Further, the non-volatile storage element has an interfacial layer constituted by a single layer film or a multiple layer film between the first conductive layer and the ferroelectric layer, the interfacial layer as a whole has permittivity higher than that of a silicon oxide, and the interfacial layer is present between the first conductive layer and the buffer layer when the buffer layer is present between the first conductive layer and the ferroelectric layer. The non-volatile storage device is at least provided with a control circuit, and a memory cell array formed by two-dimensionally or three-dimensionally arranging ferroelectric storage elements having low power consumption. The ferroelectric layer, which can be scaled to 10 nm or less, is manufactured at a low temperature of 400˚C or less and is subjected to low-temperature thermal annealing at 400˚C or less after formation of the buffer layer to improve reliability.
(FR)
La présente invention fournit un élément de stockage non volatil et un dispositif de stockage non volatil qui utilisent un matériau ferroélectrique, peuvent être incorporés dans une logique CMOS avancée, et sont excellents en termes de faible consommation d'énergie et de fiabilité élevée, et en particulier dans l'endurance de réécriture de données. L'élément de stockage non volatil comporte au moins une première couche conductrice, une seconde couche conductrice, et une couche ferroélectrique qui est constituée d'un oxyde métallique et qui est située entre les première et seconde couches conductrices, et une couche tampon présentant une conductivité des ions d'oxygène est présente entre la couche ferroélectrique et la première couche conductrice et/ou la seconde couche conductrice. En outre, l'élément de stockage non volatil comporte une couche interfaciale constituée d'un film monocouche ou d'un film multicouche entre la première couche conductrice et la couche ferroélectrique, la couche interfaciale dans son ensemble présente une permittivité supérieure à celle d'un oxyde de silicium, et la couche interfaciale est présente entre la première couche conductrice et la couche tampon lorsque la couche tampon est présente entre la première couche conductrice et la couche ferroélectrique. Le dispositif de stockage non volatil est au moins pourvu d'un circuit de commande, et d'un réseau de cellules de mémoire formé par agencement bidimensionnel ou tridimensionnel d'éléments de stockage ferroélectriques présentant une faible consommation d'énergie. La couche ferroélectrique, qui peut être mise à l'échelle à 10 nm ou moins, est fabriquée à une basse température inférieure ou égale à 400 °C et est soumise à un recuit thermique à basse température inférieure ou égale à 400 °C après la formation de la couche tampon pour améliorer la fiabilité.
(JA)
本発明は、先端CMOSロジックに混載可能な低消費電力、高信頼性、特にデータ書換え特性に優れた強誘電体材料を用いた不揮発性記憶素子及び不揮発性記憶装置を提供する。不揮発性記憶素子は、第1の導電層と、第2の導電層と、両導電層の間の金属酸化物から構成される強誘電体層とを少なくとも有し、強誘電体層と第1の導電層及び/又は第2の導電層との間に酸素イオン導電性を持つバッファ層が存在する。また、第1の導電層と強誘電体層の間に、単層膜または多層膜から構成される界面層を有し、界面層全体として酸化シリコンより高い誘電率を有し、界面層は、第1の導電層と強誘電体層の間にバッファ層が存在する場合には、第1の導電層とバッファ層の間に存在する。不揮発性記憶装置は、低消費電力の強誘電体記憶素子が2次元または3次元に配置されて形成されるメモリセルアレイと、制御回路とを少なくとも具備する。10nm以下にスケーリング可能な強誘電体層は400℃以下の低温で作製し、バッファ層形成後に400℃以下の低温熱アニール処理をして高信頼性化する。
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