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1. WO2021081196 - RING TRANSPORT EMPLOYING CLOCK WAKE SUPPRESSION

Publication Number WO/2021/081196
Publication Date 29.04.2021
International Application No. PCT/US2020/056851
International Filing Date 22.10.2020
IPC
G06F 1/3237 2019.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of a power-saving mode
3234Power saving characterised by the action undertaken
3237by disabling clock generation or distribution
G06F 1/3228 2019.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of a power-saving mode
3206Monitoring of events, devices or parameters that trigger a change in power modality
3228Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
G06F 1/04 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
CPC
G01R 31/2896
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
2851Testing of integrated circuits [IC]
2896Testing of IC packages; Test features related to IC packages
G01R 31/318552
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
317Testing of digital circuits
3181Functional testing
3185Reconfiguring for testing, e.g. LSSD, partitioning
318533using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
318552Clock circuits details
G06F 1/06
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
06Clock generators producing several clock signals
G06F 1/08
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
08Clock generators with changeable or programmable clock frequency
Applicants
  • ADVANCED MICRO DEVICES, INC. [US]/[US]
Inventors
  • WALKER, William L.
Agents
  • DAVIDSON, Ryan S.
Priority Data
16/659,97822.10.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) RING TRANSPORT EMPLOYING CLOCK WAKE SUPPRESSION
(FR) TRANSPORT ANNULAIRE EMPLOYANT UNE SUPPRESSION D'ACTIVATION D'HORLOGE
Abstract
(EN)
An integrated circuit (IC) device includes a ring transport having a plurality of nodes and a wire interconnect coupling the plurality of nodes in a ring. The wire interconnect including a wire to transmit clock wake signals around the ring transport in advance of data signaling representing a data packet. Each node is to switch from a clock gated state to a clocked state responsive to receiving a clock wake signal. The ring transport further includes a sleep controller coupled to a select node of the plurality of nodes. The sleep controller is to configure the select node into a clock suppression state for a specified duration responsive to identifying an idle condition on the ring transport via monitoring of the wire. While in the clock suppression state the node suppresses further transmission of any clock wake signals received at the select node.
(FR)
La présente invention concerne un dispositif de circuit intégré (CI) comprenant un transport annulaire ayant une pluralité de nœuds et une interconnexion de fil couplant la pluralité de nœuds en anneau. L'interconnexion de fils comprend un fil destiné à émettre des signaux d'activation d'horloge autour du transport annulaire à l'avance de la signalisation de données représentant un paquet de données. Chaque nœud doit passer d'un état à déclenchement d'horloge à un état synchronisé en réponse à la réception d'un signal d'activation d'horloge. Le transport annulaire comprend en outre un dispositif de commande de veille couplé à un nœud de sélection de la pluralité de nœuds. Le dispositif de commande de veille est destiné à configurer le nœud de sélection en un état de suppression d'horloge pendant une durée spécifiée en réponse à l'identification d'un état inactif sur le transport annulaire par le biais de la surveillance du fil. Pendant qu'il est dans l'état de suppression d'horloge, le nœud supprime une émission supplémentaire de quelconques signaux d'activation d'horloge reçus au niveau du nœud de sélection.
Also published as
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