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1. WO2021080695 - SUPER VIA INTEGRATION IN INTEGRATED CIRCUITS

Publication Number WO/2021/080695
Publication Date 29.04.2021
International Application No. PCT/US2020/049393
International Filing Date 04.09.2020
IPC
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
CPC
H01L 21/76816
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76801characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
76802by forming openings in dielectrics
76816Aspects relating to the layout of the pattern or to the size of vias or trenches
H01L 21/76879
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
71Manufacture of specific parts of devices defined in group H01L21/70
768Applying interconnections to be used for carrying current between separate components within a device ; comprising conductors and dielectrics
76838characterised by the formation and the after-treatment of the conductors
76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
76879by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
H01L 23/5226
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
5226Via connections in a multilevel interconnection structure
Applicants
  • QUALCOMM INCORPORATED [US]/[US]
Inventors
  • ZHU, John Jianhong
  • BAO, Junjing
  • CHEN, Jun
  • NALLAPATI, Giridhar
Agents
  • GALLARDO, Michelle
Priority Data
16/664,67725.10.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SUPER VIA INTEGRATION IN INTEGRATED CIRCUITS
(FR) INTÉGRATION DE SUPER-TROU D'INTERCONNEXION DANS DES CIRCUITS INTÉGRÉS
Abstract
(EN)
Aspects of the disclosure are directed to super via integration. In accordance with one aspect, an apparatus with super via integration in an integrated circuit including a first metal layer; a second metal layer, wherein the second metal layer is adjacent to the first metal layer; a third metal layer, wherein the third metal layer is adjacent to the second metal layer and is non-adjacent to the first metal layer; and a super via interconnecting the first metal layer and the third metal layer through a dielectric material, wherein the super via is filled with a selective metal.
(FR)
Des aspects de la divulgation concernent l'intégration de super-trou d'interconnexion Selon un aspect, la divulgation concerne un appareil ayant une intégration de super-trou d'interconnexion dans un circuit intégré comprenant une première couche métallique ; une deuxième couche métallique, la deuxième couche métallique étant adjacente à la première couche métallique ; une troisième couche métallique, la troisième couche métallique étant adjacente à la deuxième couche métallique et étant non adjacente à la première couche métallique ; et un super-trou d'interconnexion interconnectant la première couche de métal et la troisième couche métallique à travers un matériau diélectrique, le super-trou d'interconnexion étant rempli d'un métal sélectif.
Also published as
Latest bibliographic data on file with the International Bureau