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1. WO2022160139 - METHOD FOR FORMING BARRIER LAYER IN SEMICONDUCTOR STRUCTURE

Publication Number WO/2022/160139
Publication Date 04.08.2022
International Application No. PCT/CN2021/074005
International Filing Date 27.01.2021
IPC
H01L 21/768 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
H01L 27/1157 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11568characterised by the memory core region
1157with cell select transistors, e.g. NAND
H01L 27/11582 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
1158with source and drain on different levels, e.g. with sloping channels
11582the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/67 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Inventors
  • ZHOU, Peng
  • LV, Shuliang
  • MAO, Ge
  • LI, Yuan
  • SONG, Rui
Priority Data
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR FORMING BARRIER LAYER IN SEMICONDUCTOR STRUCTURE
(FR) PROCÉDÉ DE FORMATION D'UNE COUCHE BARRIÈRE DANS UNE STRUCTURE SEMI-CONDUCTRICE
Abstract
(EN) A method for forming a barrier layer in a semiconductor structure is disclosed. A substrate having a dielectric layer is provided. The dielectric layer is exposed to a precursor having a first metal, and a first ammonia treatment is performed. A first purge operation is performed, a second ammonia treatment is performed after the first purge operation, and a second purge operation is performed after the second ammonia treatment to form the barrier layer on the dielectric layer.
(FR) Un procédé de formation d'une couche barrière dans une structure semi-conductrice est divulgué. Un substrat comprenant une couche diélectrique est décrit. La couche diélectrique est exposée à un précurseur comprenant un premier métal, et un premier traitement à l'ammoniac est réalisé. Un premier fonctionnement de purge est effectué, un second traitement à l'ammoniac est effectué après le premier fonctionnement de purge, et un second fonctionnement de purge est effectué après le second traitement à l'ammoniac pour former la couche barrière sur la couche diélectrique.
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