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1. WO2022160113 - SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Publication Number WO/2022/160113
Publication Date 04.08.2022
International Application No. PCT/CN2021/073915
International Filing Date 27.01.2021
IPC
H01L 29/06 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/8238 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8238Complementary field-effect transistors, e.g. CMOS
H01L 21/762 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
76Making of isolation regions between components
762Dielectric regions
Applicants
  • 中芯北方集成电路制造(北京)有限公司 SEMICONDUCTOR MANUFACTURING NORTH CHINA (BEIJING) CORPORATION [CN]/[CN]
Inventors
  • 王金刚 WANG, Jingang
  • 隋振超 SUI, Zhenchao
Agents
  • 上海知锦知识产权代理事务所(特殊普通合伙) INTEBRIGHT LLP
Priority Data
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
(FR) STRUCTURE SEMI-CONDUCTRICE ET SON PROCÉDÉ DE FORMATION
(ZH) 半导体结构及其形成方法
Abstract
(EN) A semiconductor structure and a method for forming same, the semiconductor structure comprising: a substrate, which comprises a device unit region and an isolation region located on the periphery of the device unit region; an isolation structure, located within the substrate in the isolation region; a device gate structure, located on the substrate in the device unit region; and a source/drain doped layer, which is embedded into the substrate in the device unit region on two sides of the device gate structure, wherein the source/drain doped layer comprises a source/drain body layer, and the sidewall of the source/drain body layer located on the edge of the device unit region is spaced apart from the isolation structure. In the semiconductor structure of embodiments of the present invention, the sidewall of the source/drain body layer located on the edge of the device unit region is spaced apart from the isolation structure, such that the sidewall of the source/drain body layer located on the edge of the device unit region is not in contact with the isolation structure, which is beneficial to preventing doped ions in the source/drain body layer from diffusing into the isolation structure, and thus is beneficial to preventing an increase in the extension resistance of a device, thereby improving the length of diffusion (LOD) effect, and improving the performance of the semiconductor structure.
(FR) L'invention concerne une structure semi-conductrice et son procédé de formation, la structure semi-conductrice comprenant : un substrat, qui comprend une région d'unité de dispositif et une région d'isolation située sur la périphérie de la région d'unité de dispositif; une structure d'isolation, située à l'intérieur du substrat dans la région d'isolation; une structure de grille de dispositif, située sur le substrat dans la région d'unité de dispositif; et une couche dopée de source/drain, qui est incorporée dans le substrat dans la région d'unité de dispositif sur deux côtés de la structure de grille de dispositif, la couche dopée de source/drain comprenant une couche de corps de source/drain, et la paroi latérale de la couche de corps de source/drain située sur le bord de la région d'unité de dispositif est espacée de la structure d'isolation. Dans la structure semi-conductrice de modes de réalisation de la présente invention, la paroi latérale de la couche de corps de source/drain située sur le bord de la région d'unité de dispositif est espacée de la structure d'isolation, de telle sorte que la paroi latérale de la couche de corps de source/drain située sur le bord de la région d'unité de dispositif n'est pas en contact avec la structure d'isolation, qui est bénéfique pour empêcher des ions dopés dans la couche de corps de source/drain de se diffuser dans la structure d'isolation, et donc est bénéfique pour empêcher une augmentation de la résistance à l'extension d'un dispositif, ce qui permet d'améliorer la longueur d'effet de diffusion (LOD) et améliorer les performances de la structure semi-conductrice.
(ZH) 一种半导体结构及其形成方法,所述半导体结构包括:基底,包括器件单元区和位于器件单元区外周的隔离区;隔离结构,位于隔离区的基底内;器件栅极结构,位于器件单元区的基底上;源漏掺杂层,嵌入于器件栅极结构两侧器件单元区的基底内,源漏掺杂层包括源漏主体层,且位于器件单元区边缘的源漏主体层的侧壁与隔离结构之间相间隔。本发明实施例的半导体结构中,位于器件单元区边缘的源漏主体层侧壁与隔离结构之间相间隔,从而位于器件单元区边缘的源漏主体层的侧壁与隔离结构之间未相接触,有利于防止源漏主体层中的掺杂离子向隔离结构中扩散,进而有利于防止器件的延伸(Extension)电阻升高的问题、改善扩散区长度(LOD)效应,提升了半导体结构的性能。
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