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1. WO2021029935 - EXTENDED MEMORY INTERFACE

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Publication Number WO/2021/029935
Publication Date 18.02.2021
International Application No. PCT/US2020/034942
International Filing Date 28.05.2020
IPC
G06F 13/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 3/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from, or digital output to, record carriers
G06F 12/0806 2016.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
G06F 9/30 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
G06F 15/78 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
15Digital computers in general; Data processing equipment in general
76Architectures of general purpose stored program computers
78comprising a single central processing unit
G06F 30/34 2020.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
30Computer-aided design
30Circuit design
34for reconfigurable circuits, e.g. field programmable gate arrays or programmable logic devices
CPC
G06F 13/1668
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
G06F 13/4027
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
4004Coupling between buses
4027using bus bridges
G06F 3/0604
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0602specifically adapted to achieve a particular effect
0604Improving or facilitating administration, e.g. storage management
G06F 3/0659
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
0659Command handling arrangements, e.g. command buffers, queues, command scheduling
G06F 3/0683
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0668adopting a particular infrastructure
0671In-line storage system
0683Plurality of storage devices
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • RAMESH, Vijay S.
  • PORTERFIELD, Allan
Agents
  • GALLUS, Nathan J.
Priority Data
16/537,99812.08.2019US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) EXTENDED MEMORY INTERFACE
(FR) INTERFACE DE MÉMOIRE ÉTENDUE
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Abstract
(EN)
Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices coupled to one another. Each of the plurality of computing devices can include a processing unit configured to perform an operation on a block of data in response to receipt of the block of data. Each of the plurality of computing devices can further include a memory array configured as a cache for the processing unit. The example apparatus can further include a first plurality of communication subsystems coupled to the plurality of computing devices and to a second plurality of communication subsystems. The first and second plurality of communication subsystems are configured to request and/or transfer the block of data.
(FR)
L'invention concerne des systèmes, des appareils et des procédés ayant trait à des sous-systèmes de communication à mémoire étendue qui permettent d'exécuter des opérations de mémoire étendue. Un appareil illustratif peut comprendre une pluralité de dispositifs informatiques couplés les uns aux autres. Chacun des dispositifs de la pluralité de dispositifs informatiques peut comprendre une unité de traitement configurée de sorte à effectuer une opération sur un bloc de données en réponse à la réception du bloc de données. Chacun des dispositifs de la pluralité de dispositifs informatiques peut en outre comprendre une matrice mémoire conçue sous forme de mémoire cache pour l'unité de traitement. L'appareil illustratif peut en outre comprendre une première pluralité de sous-systèmes de communication couplés à la pluralité de dispositifs informatiques et à une seconde pluralité de sous-systèmes de communication. Les premier et second sous-systèmes de communication sont conçus pour demander et/ou transférer le bloc de données.
Also published as
US20210049116
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