WO2021003147 NEURAL NETWORK MEMORY

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Publication Number WO/2021/003147

Publication Date 07.01.2021

International Application No. PCT/US2020/040279

International Filing Date 30.06.2020

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CPC

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Applicants

MICRON TECHNOLOGY, INC. [US]/[US]

Inventors

BONIARDI, Mattia
TORTORELLI, Innocenzo

Agents

GALLUS, Nathan

Priority Data

16/503,015

03.07.2019

Publication Language English (EN)

Filing Language English (EN)

Designated States

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Title

(EN) NEURAL NETWORK MEMORY

(FR) MÉMOIRE DE RÉSEAU NEURONAL

Abstract

(EN)

An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.

(FR)

L'invention concerne un appareil donné à titre d'exemple qui peut comprendre un réseau de mémoire et un contrôleur de mémoire. Le réseau de mémoire peut comprendre une première partie comprenant une première pluralité de cellules de mémoire. Le réseau de mémoire peut en outre comprendre une seconde partie comprenant une seconde pluralité de cellules de mémoire. Le contrôleur de mémoire peut être couplé à la première partie et à la seconde partie. Le contrôleur de mémoire peut être configuré pour faire fonctionner la première pluralité de cellules de mémoire pour des opérations de mémoire à court terme. Le contrôleur de mémoire peut en outre être configuré pour faire fonctionner la seconde pluralité de cellules de mémoire pour des opérations de mémoire à long terme.

Also published as

US20210004174

Latest bibliographic data on file with the International Bureau

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
13	Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173

G	PHYSICS
06	COMPUTING; CALCULATING OR COUNTING
N	COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3	Computer systems based on biological models
02	using neural network models
06	Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063	using electronic means

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
13	Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173

G	PHYSICS
06	COMPUTING; CALCULATING OR COUNTING
N	COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3	Computer systems based on biological models
02	using neural network models
06	Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063	using electronic means

G	PHYSICS
06	COMPUTING; CALCULATING; COUNTING
F	ELECTRIC DIGITAL DATA PROCESSING
3	Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06	Digital input from or digital output to record carriers ; , e.g. RAID, emulated record carriers, networked record carriers
0601	Dedicated interfaces to storage systems
0602	specifically adapted to achieve a particular effect
0604	Improving or facilitating administration, e.g. storage management

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1. WO2021003147 - NEURAL NETWORK MEMORY

WIPO Translate

H	ELECTRICITY
01	BASIC ELECTRIC ELEMENTS
L	SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27	Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02	including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04	the substrate being a semiconductor body
10	including a plurality of individual components in a repetitive configuration
105	including field-effect components
112	Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115	Electrically programmable read-only memories; Multistep manufacturing processes therefor
11502	with ferroelectric memory capacitors

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
13	Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002	using resistive RAM [RRAM] elements
0009	RRAM elements whose operation depends upon chemical change
0011	comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
13	Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002	using resistive RAM [RRAM] elements
0021	Auxiliary circuits
004	Reading or sensing circuits or methods
0047	Read destroying or disturbing the data

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
2213	Indexing scheme relating to G11C13/00 for features not covered by this group
30	Resistive cell, memory material aspects

G	PHYSICS
11	INFORMATION STORAGE
C	STATIC STORES
2213	Indexing scheme relating to G11C13/00 for features not covered by this group
70	Resistive array aspects
71	Three dimensional array