Processing

Please wait...

Settings

Settings

Goto Application

1. WO2021001918 - OPTICAL MODULATOR

Publication Number WO/2021/001918
Publication Date 07.01.2021
International Application No. PCT/JP2019/026255
International Filing Date 02.07.2019
IPC
G02F 1/015 2006.01
GPHYSICS
02OPTICS
FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01for the control of the intensity, phase, polarisation or colour
015based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction
Applicants
  • 日本電信電話株式会社 NIPPON TELEGRAPH AND TELEPHONE CORPORATION [JP]/[JP]
Inventors
  • 開 達郎 HIRAKI, Tatsuro
  • 松尾 慎治 MATSUO, Shinji
  • 土澤 泰 TSUCHIZAWA, Tai
Agents
  • 山川 茂樹 YAMAKAWA, Shigeki
  • 小池 勇三 KOIKE, Yuzo
  • 山川 政樹 YAMAKAWA, Masaki
  • 本山 泰 MOTOYAMA, Yasushi
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) OPTICAL MODULATOR
(FR) MODULATEUR OPTIQUE
(JA) 光変調器
Abstract
(EN)
The present invention comprises: a core (102) formed on a lower clad layer (101) and composed of an amorphous undoped semiconductor (i-type); a p-type layer (103) and an n-type layer (104) which are disposed on the lower clad layer (101) with the core (102) interposed therebetween, and formed in contact with the core (102). The core (102) is formed thicker than the p-type layer (103) and the n-type layer (104). The p-type layer (103) and the n-type layer (104) are composed of a single crystal silicon.
(FR)
La présente invention comprend : un noyau (102) formé sur une couche de revêtement inférieure (101) et composé d'un semi-conducteur non dopé amorphe (type i) ; une couche de type p (103) et une couche de type n (104) qui sont disposées sur la couche de revêtement inférieure (101) avec le noyau (102) intercalé entre celles-ci, et formées en contact avec le noyau (102). Le noyau (102) est formé plus épais que la couche de type p (103) et la couche de type n (104). La couche de type p (103) et la couche de type n (104) sont composées d'un silicium monocristallin.
(JA)
下部クラッド層(101)の上に形成された、非晶質のアンドープの半導体(i型)からなるコア(102)と、下部クラッド層(101)の上で、コア(102)を挾んで配置され、コア(102)に接して形成されたp型層(103)およびn型層(104)とを備える。コア(102)は、p型層(103)およびn型層(104)より厚く形成されている。p型層(103)およびn型層(104)は、単結晶シリコンから構成されている。
Latest bibliographic data on file with the International Bureau