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1. WO2020102291 - METHOD FOR MAKING A FINFET HAVING REDUCED CONTACT RESISTANCE

Publication Number WO/2020/102291
Publication Date 22.05.2020
International Application No. PCT/US2019/061102
International Filing Date 13.11.2019
IPC
H01L 29/66 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
H01L 29/417 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
41characterised by their shape, relative sizes or dispositions
417carrying the current to be rectified, amplified or switched
H01L 29/45 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
43characterised by the materials of which they are formed
45Ohmic electrodes
Applicants
  • ATOMERA INCORPORATED [US]/[US]
Inventors
  • TAKEUCHI, Hideki
  • CONNELLY, Daniel
  • HYTHA, Marek
  • BURTON, Richard
  • MEARS, Robert J.
Agents
  • REGAN, Christopher F.
  • WARTHER, Richard K.
  • WOODSON, II, John F.
  • TAYLOR, Michael W.
  • ABID, Jack G.
  • CARUS, David S.
  • MCKINNEY, Matthew G.
Priority Data
16/192,91116.11.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR MAKING A FINFET HAVING REDUCED CONTACT RESISTANCE
(FR) PROCÉDÉ DE FABRICATION D'UN FINFET DOUÉ D'UNE UNE RÉSISTANCE DE CONTACT RÉDUITE
Abstract
(EN)
A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.
(FR)
La présente invention porte sur un procédé de fabrication d'un FinFET pouvant consister à former des régions de source et de drain espacées dans une ailette semi-conductrice, une région de canal s'étendant entre ces dernières. La région de source et/ou la région de drain peuvent être divisées en une région inférieure et une région supérieure par un super-réseau de blocage de diffusion de dopant, la région supérieure ayant une conductivité identique et une concentration de dopant supérieure à la région inférieure. Le procédé peut en outre consister à former une grille sur la région de canal, à déposer au moins une couche métallique sur la région supérieure, et à appliquer de la chaleur afin de déplacer vers le haut des atomes non semi-conducteurs des monocouches non semi-conductrices de façon à réagir avec ladite couche métallique ou à former une interface d'isolation de contact entre la région supérieure et des parties adjacentes de ladite couche métallique.
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